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datasheet frequency timing gene rator for peripherals 9fgp202a idt? frequency timing generator for peripherals 1 9fgp202a rev d 070511 general description the 9fgp202a is a peripheral clock for intel server. it is driven with a 25mhz crystal and generates cpu outputs up to 400mhz. an smbus interface allows full control of the device. recommended application peripheral clock for intel server output features ? 1 - 0.7v current-mode differential cpu pair ? 8 - 50mhz output ? 1 - dot 96mhz output ? 1 - 33.33mhz output ? 1 - 32.768khz output ? 2 - 25mhz ref outputs features/benefits ? selectable smbus address ? d0/d1 or c0/c1 ? spread spectrum capabilit y on cpu and dot 96mhz clocks ? smbus control: ? m/n and spread programming on cpu and dot 96mhz clocks via smbus ? outputs can be disabled via pins or smbus key specifications ? exact synthesis on cpu, rmii and 33.33mhz clocks ? +/- 100ppm frequency accuracy on remaining clocks block diagram x1_25 x2_25 cpuclk control logic oe_rmiib smbdat smbclk smbadr cpu pll (spread capable) oe_cpu oe_rmiia dot96ss dot pll (spread capable) fixed pll xtal dividers oe_96 8 vttpwr_gd/pd# 33.33mhz rmii(7:0) 32.768khz 25mhz(1:0) dividers
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 2 9fgp202a rev d 070511 pin configuration smbus address selection power supply pins functionality vttpwr_gd/pd# smbdat smbclk rmii0 rmii1 gnd rmii vddrmii rmii2 rmii3 oe_rmiia 40 39 38 37 36 35 34 33 32 31 gnd 130 oe _rmi ib vdd9 6 229 rmii4 dot96sst 328 rmii5 dot96ssc 427 gnd rmii oe_96 526 vddrm ii oe _cp u 625 rmii6 cpuclkt0 724 rmii7 cpuclkc0 823 vdd33 vddcpu 922 33.33mhz/**smbad r gndcpu 10 21 gnd 33 11 12 13 14 15 16 17 18 19 20 iref vdd32k 32.768khz gnd32k vdd ref 25mhz_0 25mhz_1 gndref x1_25 x2_25 9fgp202 40-mlf * internal pull-up resistor ** internal pull-down resistor *smbadr = 0 smbadr = 1 d0/d1 c0/c1 * default value smbadr vd d gnd 9 10 cpuclk output 2 1 dot96ss output 26,34 27,35 50 mhz rmii outputs 23 21 33.33mhz output 12 14 32.768khz output 15 18 xtal, ref outputs description pi n number note: all vdd should be connected to a common power rail with proper filtering and decoupling. cpu fs2 cpu fs1 cpu fs0 byte0 bit2 byte0 bit1 byte0 bit0 0 0 0 266.67 96.00 33.33 50.00 25.00 32.768 0 0 1 133.33 96.00 33.33 50.00 25.00 32.768 0 1 0 200.00 96.00 33.33 50.00 25.00 32.768 0 1 1 166.67 96.00 33.33 50.00 25.00 32.768 1 0 0 333.33 96.00 33.33 50.00 25.00 32.768 1 0 1 100.00 96.00 33.33 50.00 25.00 32.768 1 1 0 400.00 96.00 33.33 50.00 25.00 32.768 1 1 1 reserved 96.00 33.33 50.00 25.00 32.768 p ower up default is highlighted. 32.768 khz cpuclk mhz dot96ss mh z 33.33 mhz rmii mh z 25 mhz
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 3 9fgp202a rev d 070511 pin descriptions pin # pin name pin type desc ription 1 gnd pwr ground p in. 2 vdd96 pwr power p in for the dot9 6 cl oc ks, no mi na l 3 .3v 3 dot96sst out true clock of differential pair for 96.00mhz spread spectrum capable dot clock. 4 dot96ssc out complement clock of differential pair for 96.00mhz spread spectrum capable dot clock. 5oe_96 in active high input for enabling 96hz outputs. 1 = enable out p ut ( s ) , 0 = tri-state out p ut ( s ) 6oe_cpu in active high input for enabling cpu diff pairs. 1 = enable out p ut ( s ) , 0 = tri-state out p ut ( s ) 7cpuclkt0 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are requir ed for voltage bi as . 8cpuclkc0 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are re q ui red for volta g e bias. 9 vdd cpu pwr su pp l y for cpu clocks, 3.3v nominal 10 gnd cpu p w r gro un d p i n for the cpu out p uts 11 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 12 vdd32k pwr power pin for the 32.768khz outputs, nominal 3.3v 13 32.768khz out 32.768khz clock out p ut 14 gnd32k pwr ground p in for the 32.768khz out p uts 15 vddref pwr ref, xtal p ower su pp l y , nominal 3.3v 16 25mhz_0 out 25mhz clock output, 3.3v 17 25mhz_1 out 25mhz clock output, 3.3v 18 gndref pwr ground pin for the ref outputs. 19 x1_25 in crystal input, nominally 25.00mhz. 20 x2 _25 out cr y stal out p ut, nominall y 25.00mhz. 21 gnd33 pwr ground p in for the 33.33mhz out p uts 22 33.33mhz/**smbadr i/o 33.33mhz clock output / smbus address select bit. 23 vdd33 pwr power pin for the 33.33mhz outputs, nominal 3.3v 24 rmii7 out 3.3v rmii clock output 25 rmii6 out 3.3v rmii clock output 26 vdd rmii p w r 3.3 v p ower p in for the rmii clocks. 27 gndrmii pwr ground p in for the 3v50 out p uts 28 rmii5 out 3.3v rmii clock output 29 rmii4 out 3.3v rmii clock output 30 oe_rmiib in active high input for enabling rmii(7:4) outputs. 1 = enable out p ut ( s ) , 0 = low 31 oe_rmiia in active high input for enabling rmii(3:0) outputs. 1 = enable out p ut ( s ) , 0 = low 32 r mii 3 out 3.3v rmii clock out p ut 33 rmii2 out 3.3v rmii clock output 34 vddrmii pwr 3.3v power pin for the rmii clocks. 35 gndrmii pwr ground pin for the 3v50 outputs 36 rmii1 out 3.3v rmii clock out p ut 37 rmii0 out 3.3v rmii clock out p ut 38 smbclk in clock p in of smbus circuitr y , 5v tolerant 39 smbdat i/o data pin of smbus circuitry, 5v tolerant 40 vttpwr_gd/pd# in this 3.3v lvttl input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. this is an active high input. / asynchronous active low input pin used to power down the devic e into a low pow er state.
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 4 9fgp202a rev d 070511 drive strengths the singled-ended outputs of the 9fgp202a default to either a drive strength of 2 loads or a drive strength of 1 load. alternate drive strengths can be selected via the smbus. using the correct resistor value can properly terminate the output to the transmission line without having to change the default drive strengths via the smbus. the default drive strengths for the single ended outputs are show below, as are the suggeste d termination resistors for the above topologies. all values assume zo = 50 ohms: 9fgp202a series termination resistor values output drive strength series resistor (rs) for driving 1 load series resistor (rs) for driving 2 loads 1 load 33 ohms n /a 2 loads 43 ohms 22 ohms default drive stren g th table default drive optional drive rmii 1 load 2 loads 33.33mhz 2 loads 1 load 25mhz 2 loads 1 load 32.768khz 2 loads 1 load
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 5 9fgp202a rev d 070511 truth table 1: vttpwr_gd/pd# and oe_96 vttpwr_gd/pd# oe_96 pin 40 pin 5 0 0 all clocks are powered down 0 1 all clocks are powered down 1 0 all clocks are enabled except dot96ss 1 1 *all clocks are enabled including dot96ss *assuming dot96 output enable from smbus byte2 bit0 sets to enable (default) clocks truth table 2: vttpwr_gd/pd# and oe_cpu vttpwr_gd/pd# oe_cpu pin 40 pin 6 0 0 all clocks are powered down 0 1 all clocks are powered down 1 0 all clocks are enabled except cpuclk 1 1 *all clocks are enabled including cpuclk *assuming cpuclk output enable from smbus byte2 bit1 sets to enable (default) clocks table 1: cpu spread and frequency selection cpu ss _ e n cpu fs2 cpu fs1 cpu fs0 byte 0 bit 3 byte 0 bit 2 byte 0 bit 1 byte 0 bit 0 0 0 0 0 266.67 0% 0 0 0 1 133.33 0% 0 0 1 0 200.00 0% 0 0 1 1 166.67 0% 0 1 0 0 333.33 0% 0 1 0 1 100.00 0% 0 1 1 0 400.00 0% 0 1 1 1 200.00 0% 1 0 0 0 266.67 0.5% 1 0 0 1 133.33 0.5% 1 0 1 0 200.00 0.5% 1 0 1 1 166.67 0.5% 1 1 0 0 333.33 0.5% 1 1 0 1 100.00 0.5% 1 1 1 0 400.00 0.5% 1 1 1 1 200.00 0.5% cpu mh z do wn sp rea d %
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 6 9fgp202a rev d 070511 table2: dot96 spread and frequency selection table dot96 ss_ en fs3 fs2 fs1 fs0 byte 0 bit 4 byte 3 bit 3 byte 3 bit 2 byte 3 bit 1 byte 3 bit 0 0000096.00 0000196.00 0001096.00 0001196.00 0010096.00 0010196.00 0011096.00 0011196.00 0100096.00 0100196.00 0101096.00 0101196.00 0110096.00 0110196.00 0111096.00 0111196.00 1000096.00+/-0.25center 1 0 0 0 1 96.00 +/-0.5 center 1001096.00+/-0.75center 1 0 0 1 1 96.00 +/-1.0 center 1010096.00-0.25down 1010196.00-0.50down 1011096.00-0.75down 1011196.00-1.0down 1100096.00-1.25down 1100196.00-1.50down 1101096.00-1.75down 1101196.00-2.0down 1110096.00 -2.25 down 1110196.00-2.5down 1111096.00-2.75down 1111196.00 -3.00 down 0 0 0 0 0 0 0 0 0 0 0 0 dot96ss mhz spread % 0 0 0 0
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 7 9fgp202a rev d 070511 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9fgp202a. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical pa rameters are guaranteed only over the recommended operating temperature range. electrical characteristics?dot96ss 0.7v current mode differential pair parameter symbol conditions min typ max units notes 3.3v supply voltage vddxxx - gnd - 0.5 3.3v gnd + 4.5 v 1 maxi mum difference across all vdd p ins vdddelta - 0.5 v 1 storage temperature ts - -65 150 c 1 ambient operating temp tambient - 070c 1 junction temperature tj - 125 c 1 input esd protection hbm esd pro t - 2000 v 1 1 guaranteed by desig n and characterization, not 100% tested in production. p aramete r symb ol conditions* min typ max units notes current source output impedance zo v o = v x 3000 ? 1 voltage high vhigh 660 850 mv 1,3 voltage low vlow -150 150 mv 1,3 max voltage vovs 1150 mv 1 min voltage vuds -300 mv 1 crossing voltage (abs) vx(abs) 250 550 mv 1 crossing voltage (var) d-vcross v ariation of crossing over a ll ed g es 140 mv 1 long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 96.00mhz nominal 10.4135 10.4198 ns 2 96.00mhz spread 10.4135 10.4722 ns 2 absolute min period tabsmin 96.00mhz no minal/spread 10.1635 10.7222 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r v ol = 0.175v, v oh = 0.525v 125 ps 1 fall time variati on d-t f v oh = 0.525v v ol = 0.175v 125 ps 1 duty cycle d t3 measure ment from differential wav ef rom 45 55 % 1 j itt er, c yc le t o cy cle t jcyc -cyc measure ment from differential wav ef rom 250 ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5% ; c l =2pf, r s =33.2 ohms , r p =49.9 ohms , i ref = 475 ohms 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout is at 25.00mhz 3 i ref = v dd /(3xr r ). for r r = 475ohms (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50ohms. measurement on single ended signal using absolute value. statistical measu rement on singl e ended signal average period tperiod
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 8 9fgp202a rev d 070511 electrical characteristics?input/ supply/common output parameters p aramete r symb ol conditions* min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua 1 i il 1 v in = 0 v; inputs with no pull-up resistors -5 ua 1 i il 2 v in = 0 v ; inputs with pull-up resistors -200 ua 1 low thresh old input- hi g h volta g e v ih_fs 3.3 v +/-5% 0.7 v dd + 0.3 v 1 low thresh old input- low volta g e v il _f s 3.3 v +/-5% v ss - 0.3 0.35 v 1 operating current i dd 3. 3o p all outputs driven 200 ma 1 all diff pairs driven 30 ma 1 all differential pairs tri-stated 8 ma 1 input frequency f i v dd = 3.3 v 25.00000 mhz 2 pin inductance l pi n 7nh1 c in logic inputs 4 pf 1 c ou t output pin capacitance 5 pf 1 c inx x1 & x 2 pins 5 pf 1 clk stabiliza tion t stab from v dd power-up or de- assertion of pd to 1st clock 2.5 ms 1 modulation frequency triangular modulation 30 33 khz 1 tdrive_pd cp u output enable after pd de-assertion 300 us 1 t fall_ pd pd f all tim e of 5 ns 1 trise_pd pd rise time of 5 ns 1 smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ol @ i pul lup 0.4 v 1 current sinking at v ol = 0.4 v i pu llu p 4ma1 sclk/sdata clock/data rise time t ri 2c (max vil - 0.15) to ( min vih + 0.15 ) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min v ih + 0.15) to (max vil - 0.15) 300 ns 1 *ta = 0 - 70c; s upply voltage vdd = 3.3 v +/-5% 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 input frequ ency should be measured at the ref pin and tuned to ideal 25.00mhz to meet ppm frequency accuracy on pll outputs. input l ow current powerdow n current i dd 3. 3pd input capacitance
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 9 9fgp202a rev d 070511 electrical characteristics?cpu 0.7v current mode differential pair p aramete r symb ol conditions* min typ max units notes current source output impedance zo v o = v x 3000 ? 1 voltage high vhigh 660 850 mv 1,3 voltage low vlow -150 150 mv 1,3 max voltage vovs 1150 mv 1 min voltage vuds -300 mv 1 crossing voltage (abs) vx(abs) 250 550 mv 1 crossing voltage (var) d-vx v ariation of crossing over a ll ed g es 140 mv 1 long accuracy ppm see tperiod min-max values -100 0 100 ppm 1,2 400mhz nomin al 2.4998 2.5000 2.5003 ns 2 400mhz sp rea d 2.4998 2.5128 ns 2 333.33mhz nominal 2.9997 3.0000 3.0003 ns 2 333.33mhz spread 2.9997 3.0154 ns 2 266.66mhz nominal 3.7496 3.7500 3.7504 ns 2 266.66mhz spread 3.7496 3.7692 ns 2 200mhz nomin al 4.9995 5.0000 5.0005 ns 2 200mhz sp rea d 4.9995 5.0256 ns 2 166.66mhz nominal 5.9994 6.0000 6.0006 ns 2 166.66mhz spread 5.9994 6.0307 ns 2 133.33mhz nominal 7.4993 7.5000 7.5008 ns 2 133.33mhz spread 7.4993 7.5385 ns 2 100.00mhz nominal 9.9990 10.0000 10.0010 ns 2 100.00mhz spread 9.9990 10.0513 ns 2 400mhz nominal/spread 2.4148 2.5978 ns 1,2 333.33mhz nominal/spread 2.9147 3.1004 ns 1,2 266.66mhz nominal/spread 3.6646 3.8542 ns 1,2 200mhz nominal/spread 4.9145 5.1106 ns 1,2 166.66mhz nominal/spread 5.9144 6.1157 ns 1,2 133.33mhz nominal/spread 7.4143 7.6235 ns 1,2 100.00mhz nominal/spread 9.9140 10.1363 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r v ol = 0.175v, v oh = 0.525v 125 ps 1 fall t ime variati on d-t f v oh = 0.525v v ol = 0.175v 125 ps 1 dut y cy c le d t3 measure ment from differential wav ef rom 45 55 % 1 j itt er, c yc le t o cy cle t jcyc -cyc measure ment from differential wavefrom , cpuclk 85 ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5% ; c l =2pf, r s =33.2ohms, r p =49.9ohms, i ref = 475ohms 1 guaranteed by desig n and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 25.000mhz 3 i ref = v dd /(3xr r ). for r r = 475ohms (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50ohms. statistical measu rement on singl e ended signal measurement on single ended signal using absolute value. average period tperiod absolute min/ma x period t ab smin /ma x
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 10 9fgp202a rev d 070511 electrical characteristics?rmii - 50mhz electrical characteristics?33.33mhz parameter symbol conditions* min typ max units notes long accuracy ppm see tperiod min-max values -50 0 50 ppm 1,2 clock period tperiod 50.00mhz output nominal 19.990 20.000 20.010 ns 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rise time t r v ol = 0.4 v , v oh = 2.4 v 1 3 ns 1 fall time t f v oh = 2.4 v , v ol = 0.4 v 1 3 ns 1 dut y c yc le d t1 v t = 1.5 v 35 65 % 1 t skew _3 v50(3 : 0) t skew _3 v50(7 : 4) jitter, long term t jabs v t = 1.5 v, 10 sec interval 500 ps 1 ji tt er, peak t jpe ak v t = 1.5 v 100 ps 1,3 *ta = 0 - 70c; s upply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs as shown i n the termination table (unless otherwise specif ied) 1 guaranteed by desig n and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 25.00mhz 3 1/2 of the peak-to-peak jitte r. (lg+ + |lg-|)/2 200 ps 1 group s kew v t = 1.5 v, for each group of 4 outputs output high current i oh output low current i ol p aramete r symb ol conditions* min typ max units notes long accuracy ppm see tperiod min-max values -1 00 0 100 ppm 1 clock period tperiod 33.33mhz output non-spread 29.970 30.000 30.030 ns 1 absolute min/ma x period tabs 33.33mhz output non-spread 29.720 30.000 30.280 ns 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rise time t r v ol = 0.4 v , v oh = 2.4 v 0.5 2 ns 1 fall time t f v oh = 2.4 v , v ol = 0.4 v 0.5 2 ns 1 dut y c yc le d t1 v t = 1.5 v 45 55 % 1 j itt er, c yc le t o cy cle t jcyc -cyc v t = 1.5 v 250 ps 1 *ta = 0 - 70c; s upply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs as shown i n the termination table (unless otherwise specif ied) 1 guaranteed by desig n and characterization, not 100% tested in production. output high current i oh output low current i ol
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 11 9fgp202a rev d 070511 electrical characteristics?32.768khz electrical characteristics?ref - 25mhz parameter symbol conditions* min typ max units notes long accuracy ppm see tperiod min-max values -1 00 100 ppm 1 clock period tperiod 32.768khz output nominal 30.518 us 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rise time t r v ol = 0.4 v , v oh = 2.4 v 1 4 ns 1 fall time t f v oh = 2.4 v , v ol = 0.4 v 1 4 ns 1 dut y c yc le d t1 v t = 1.5 v 45 55 % 1 j itt er, c yc le t o cy cle t jcyc -cyc v t = 1.5 v 500 ps 1 *ta = 0 - 70c; s upply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs as shown i n the termination table (unless otherwise specif ied) 1 guaranteed by desig n and characterization, not 100% tested in production. output high current i oh output low current i ol parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -50 50 ppm 1,2 clock period t pe rio d 25.00mhz output nominal 39.980 40.000 40.020 ns 2 outp ut high volta ge v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 2 ns 1 skew t sk1 v t = 1.5 v 500 ps 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 ji tt er t jcyc -cyc v t = 1.5 v 500 ps 1 *ta = 0 - 70c; s upply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs as shown i n the termination table (unless otherwise specif ied) 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout is at 25.000mhz i ol output low current i oh output high current
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 12 9fgp202a rev d 070511 general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit * by default, smbadr = 0, therefore, smbus write/read address is d0/d1. please see smbus address selection table on page 2. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit read address write address *d1 (h) *d0 (h) index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 13 9fgp202a rev d 070511 smbus table: cpu frequency select and spread spectrum control register byte 0 name control function type 0 1 pwd bit 7 reserved reserved rw 0 bit 6 reserved reserved rev 0.20 0 bit 5 reserved reserved rw 0 bit 4 dot96 ss_en dot96 spread spectrum enable rw d isable enable 0 bit 3 cpu ss_en cpu spread spectrum enable rw 0 bit 2 cpu fs2 cpu freq select bit 2 rw 0 bit 1 cpu fs1 cpu freq select bit 1 rw 1 bit 0 cpu fs0 cpu freq select bit 0 rw 0 smb us table: rmii output control r egister byte 1 name control function type 0 1 pwd bit 7 rmii_7 enable rmii_7 output control rw d isable enable 1 bit 6 rmii_6 enable rmii_6 out p ut control rw disable enable 1 bit 5 rmii_5 enable rmii_5 out p ut control rw disable enable 1 bit 4 rmii_4 enable rmii_4 out p ut control rw disable enable 1 bit 3 rmii_3 enable rmii_3 out p ut control rw disable enable 1 bit 2 rmii_2 enable rmii_2 out p ut control rw disable enable 1 bit 1 rmii_1 enable rmii_1 out p ut control rw disable enable 1 bit 0 rmii_0 enable rmii_0 output control rw d isable enable 1 smb us table: dot, cpu, 32.768k hz, 25mhz and 33.33mhz outputs control r egister byte 2 name control function type 0 1 pwd bit 7 cpuclk pd drive mode driven in pd rw driven hi-z 0 bit 6 dot96ss pd drive mode driven in pd rw driven hi-z 0 bit 5 33.33mh z enable 33.33mhz output control rw d isable enable 1 bit 4 25mhz_1 enable 25mhz_1 output control rw disable enable 1 bit 3 25mhz_0 enable 25mhz_0 output control rw disable enable 1 bit 2 32.768khz enable 32.768khz output control rw d isable enable 1 bit 1 cpuclk enab le cpuclk output control rw d isable enable 1 bit 0 dot96ss enable d ot96ss output control rw d isable enable 1 smb us table: dot96 frequency select and spread spectrum control register byte 3 name control function type 0 1 pwd bit 7 reserved reserved rw 0 bit 6 reserved reserved rw 0 bit 5 reserved reserved rw 0 bit 4 reserved reserved rw 0 bit 3 dot96ss fs3 dot96 freq select bit 3 rw 0 bit 2 dot96ss fs2 dot96 freq select bit 2 rw 0 bit 1 dot96ss fs1 dot96 fre q select bit 1 rw 0 bit 0 dot96ss fs0 dot96 freq select bit 0 rw 0 smbus table: rmii strength control register byte 4 name control function type 0 1 pwd bit 7 rmii _7 str rmii_7 strength co ntrol rw 1 -l oad (1 x) 2-loads (2x) 0 bit 6 rmii _6 str rmii_6 strength co ntrol rw 1 -l oad (1 x) 2-loads (2x) 0 bit 5 rmii _5 str rmii_5 strength co ntrol rw 1 -l oad (1 x) 2-loads (2x) 0 bit 4 rmii _4 str rmii_4 strength co ntrol rw 1 -l oad (1 x) 2-loads (2x) 0 bit 3 rmii _3 str rmii_3 strength co ntrol rw 1 -l oad (1 x) 2-loads (2x) 0 bit 2 rmii _2 str rmii_2 strength co ntrol rw 1 -l oad (1 x) 2-loads (2x) 0 bit 1 rmii _1 str rmii_1 strength co ntrol rw 1 -l oad (1 x) 2-loads (2x) 0 bit 0 rmii _0 str rmii_0 strength co ntrol rw 1 -l oad (1 x) 2-loads (2x) 0 smb us table: 32.768k hz, 25mhz and 33.33mhz strength control registe r byte 5 name control function type 0 1 pwd bit 7 reserved reserved rw reserved 0 bit 6 reserved reserved rw reserved 0 bit 5 33.33mhz str 33.33mh z stren g th control rw 1-load ( 1x ) 2-loads ( 2x ) 1 bit 4 25mhz_1 st r 25mh z_1 stren g th control rw 1-load ( 1x ) 2-loads ( 2x ) 1 bit 3 25mhz_0 st r 25mh z_1 stren g th control rw 1-load ( 1x ) 2-loads ( 2x ) 1 bit 2 32.768khz str 32.768khz stren g th control rw 1-load ( 1x ) 2-loads ( 2x ) 1 bit 1 reserved reserved rw reserved 0 bit 0 reserved reserved rw reserved 0 25 - - 37 7,8 - 3,4 22 17 - - - pin # 28 29 32 33 16 - reserved - reserved reserved - - 24 36 - - - 13 - 6 5 - - 32 29 28 25 reserved reserved see table 2: dot frequency selection table 33 reserved see table 1: cpu frequency selection table - - 22 17 16 13 - - 24 pin # reserved pin # pin # pin # pin # 37 36
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 14 9fgp202a rev d 070511 smbus table: vendor & revision id register byte 6 name control function type 0 1 pwd bit 7 rid3 r - - x bit 6 rid2 r - - x bit 5 rid1 r - - x bit 4 rid0 r - - x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smb us table: device id byte 7 name control function type 0 1 pwd bit 7 device id 7 (msb) rw 0 bit 6 device id 6 rw 0 bit 5 device id 5 rw 1 bit 4 device id 4 rw 0 bit 3 device id 3 rw 0 bit 2 device id 2 rw 0 bit 1 device id 1 rw 1 bit 0 device id 0 (lsb) rw 0 smbus table: byte count register byte 8 name control function type 0 1 pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 1 bit 2 bc2 rw - - 0 bit 1 bc1 rw - - 0 bit 0 bc0 rw - - 1 smb us table: reserved byte 9 name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smb us table: plls m/n programming enable register byte 10 name control function type 0 1 pwd bit 7 m/n_en plls m/n programming enable rw d isable enable 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: cpu pll vco frequency control register byte 11 name control function type 0 1 pwd bit 7 n div8 n divider pro g bit 8 rw x bit 6 n div 9 n divider pro g bit 9 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x reserved reserved m divider programming bits - - - pin # - pin # - pin # reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved the decimal representation of m and n divier in byte 11 and 12 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] reserved reserved - - - - - - - - revision id - - vendor id - - - - - pin # - - - - - - reserved reserved - writing t o this reg ister configures how many bytes will be read back. - - - - - - pin # device id reserved reserved reserved reserved reserved reserved pin #
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 15 9fgp202a rev d 070511 smbus table: cpu pll vco frequency control register byte 12 name control function type 0 1 pwd bit 7 n div7 rw x bit 6 n div6 rw x bit 5 n div5 rw x bit 4 n div4 rw x bit 3 n div3 rw x bit 2 n div2 rw x bit 1 n div1 rw x bit 0 n div0 rw x smb us table: cpu pll spread spectrum c ontrol register byte 13 name control function type 0 1 pwd bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x smb us table: cpu pll spread spectrum c ontrol register byte 14 name control function type 0 1 pwd bit 7 0 bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x smbus table: dot pll vco frequency control register byte 15 name control function type 0 1 pwd bit 7 n div8 n divider prog bit 8 rw x bit 6 n div9 n divider prog bit 9 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x smbus table: dot pll vco frequency control register byte 16 name control function type 0 1 pwd bit 7 n div7 rw x bit 6 n div6 rw x bit 5 n div5 rw x bit 4 n div4 rw x bit 3 n div3 rw x bit 2 n div2 rw x bit 1 n div1 rw x bit 0 n div0 rw x smb us table: dot pll spread spectrum control register byte 17 name control function type 0 1 pwd bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x these spread spectrum bits in byte 13 an d 14 will progra m the spread pece ntage. it is re co mmended t o use ics sprea d % ta ble for spread programming. reserved m divider programming bits - - pin # - - - - - - - - pin # - - spread spectrum programmin g b(7:0) these spread spectrum bits in byte 19 an d 20 will progra m the spread pece ntage. it is re co mmended t o use ics sprea d % ta ble for spread programming. - - - - - - - - pin # - - - - - - - - - spread spectrum programmin g b(7:0) - spread spectrum programmin g b(14:8) - pin # - - - - - these spread spectrum bits in byte 13 an d 14 will progra m the spread pece ntage. it is re co mmended t o use ics sprea d % ta ble for spread programming. - - - - - pin # the decimal representation of m and n divier in byte 17 and 18 will configure the vco frequency. default at power up = byte 0 rom t able. vco freq uency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] n divider programming b(7:0) the decimal representation of m and n divier in byte 17 and 18 will configure the vco frequency. default at power up = byte 0 rom t able. vco freq uency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] - - - - - n divider programming b(7:0) the decimal representation of m and n divier in byte 11 and 12 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] pin # -
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 16 9fgp202a rev d 070511 smb us table: dot pll spread spectrum control register byte 18 name control function type 0 1 pwd bit 7 0 bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x smb us table: reserved byte 19 name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smb us table: reserved byte 20 name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smb us table: reserved byte 21 name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved reserved reserved reserved reserved reserved reserved pin # reserved reserved reserved reserved reserved reserved pin # reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved - spread spectrum programmin g b(14:8) these spread spectrum bits in byte 19 an d 20 will progra m the spread pece ntage. it is re co mmended t o use ics sprea d % ta ble for spread programming. pin # - - - - pin # reserved - -
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 17 9fgp202a rev d 070511 package outline and package dimensions (40-pin mlf) ordering information "lf" suffix to the part number are the pb -free configuration and are rohs compliant. ?a? is the device revision designator (will not correlate with th e datasheet revision). while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. millimeters symbol min max a0.81.0 a1 0 0.05 a3 0.25 reference b 0.18 0.3 e 0.50 basic d x e basic 6.00 x 6.00 d2 min./max. 2.75 3.00 e2 min./max. 2.75 3.00 l min./max. 0.3 0.5 n d 10 n e 10 anvil singulation -- or -- sawn singulation 1 2 n e d index area top view seating plane a3 a1 c a l e2 e2 2 d2 d2 2 e c 0.08 (ref) n d & n e odd (ref) n d & n e even (n d -1)x (ref) e n 1 2 b thermal base (typ) if n d & n e are even (n e -1)x (ref) e e 2 part / order number shipping packaging package temperature 9FGP202AKLF trays 40-pin mlf 0 to +70c 9FGP202AKLFt tape and reel 40-pin mlf 0 to +70c
9fgp202a frequency timing generator for peripherals idt? frequency timing generator for peripherals 18 9fgp202a rev d 070511 revision history rev. issue date who description page # d 7/5/2011 d. chan updated datasheet template
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